A) Field
The embodiments discussed herein are directed to a semiconductor device, which may relate to a semiconductor device having pads for connection to an external circuit and for inspection.
B) Description of the Related Art
It is well known that as moisture or water contents permeate a circuit region of a semiconductor integrated circuit device, the performance of the device is degraded. In order to shield moisture permeating from a chip outer periphery, a moisture resistant ring for shielding moisture is formed along the chip outer periphery.
JP-A-2002-270608 (applicant: Fujitsu Limited) proposes a semiconductor device having a damascene wiring structure burying wiring patterns and via conductors in an interlevel insulating film, in which a moisture resistant ring disposed along an outer periphery of a chip is formed by a lamination of a via ring formed in the same level (layer) as the via conductors and a wiring ring formed in the same level (layer) as the wiring patterns.
JP-A-2004-297022 (Applicant: NEC Electronics Corporation) proposes to dispose a plurality of moisture resistant (sealing) rings along a chip outer periphery and connect the bottoms of the rings to a diffusion region of the semiconductor substrate.
JP-A-2004-297022 (Applicant: NEC Electronics Corporation) proposes to dispose a plurality of moisture resistance (sealing) rings along a chip outer periphery and connect the bottoms of the rings to a diffusion region in the semiconductor substrate.
A semiconductor integrated circuit device has pads in the same level (layer) as or above the uppermost wiring layer, on which pads probe needles are abutted for inspection or wires are bonded for connection to an external circuit. Pads have a relatively large size as compared with wiring patterns. The upper surface of each pad is exposed to allow a probe needle to be abutted thereon or a connection wire to be bonded thereto. Until a semiconductor integrated circuit device is completed, a plurality of inspections is performed, and a chip finally judged as a good chip is packaged.
When a probe needle is abutted on a pad during inspection, a crack may be formed in the pad. Even if a crack is formed, a wire can be bonded to the pad, and this chip can be used as a final product. However, the pad surface remains in an exposed state even after wire bonding so that moisture and hydrogen are likely to be permeated through the crack. As the permeated moisture and hydrogen reach wirings or oxide, chemical reaction occurs and the performance of a semiconductor device is adversely affected.
JP-A-2004-134450 (applicant: Fujitsu Limited) proposes to form a pad by an alternate lamination of a flat pad layer and a loop-shaped (tubular) via wall. Even if a crack is formed in the flat pad layer at the uppermost layer, moisture permeated into the lower portion is prevented from being diffused by a cup-shaped sealing structure constituted of the loop-shaped via wall and flat pad layer and from permeating into a circuit region.
JP-A-2005-175204 (applicant: Fujitsu Limited) proposes to dispose a first moisture resistant ring inside a pad train and a second moisture resistant ring outside the pad train. If a conductive moisture resistant ring is used, the first moisture resistant ring is cut off around a wiring portion connecting the pad.
Ferroelectric random access memories (FeRAM) are under development in recent years which use ferroelectric capacitors and store information by utilizing polarization reversal of ferroelectric material. A ferroelectric memory is a nonvolatile memory whose stored information will not be erased even if a power supply is turned off, and is expected to realize high integration, high speed driving, high durability and low power consumption.
The ferroelectric memory stores information by utilizing hysteresis characteristics of ferroelectric material. A ferroelectric capacitor sandwiching a ferroelectric film as a capacitor dielectric film between a pair of electrodes generates polarization corresponding to a voltage applied across the electrodes, and maintains the polarization even if the applied voltage is disconnected. As a polarity of an applied voltage is reversed, polarity of the polarization is also reversed. By detecting the polarization, information can be read. Mainly used as the material of ferroelectric film is ferroelectric oxide material having perovskite crystal structure and a large coercive polarization amount, e.g., 10 μC/cm2 to 30 μC/cm2, such as PZT (Pb(Zr1-xTix)O3) and SBT (SrBi2Ta2O9). In order to form an ferroelectric oxide film having excellent characteristics, the film is required to be formed or to be subjected to heat treatment in an oxidizing atmosphere. Lower electrodes (also upper electrodes if necessary) are often made of noble metal hard to be oxidized, noble metal or noble metal oxide maintaining conductivity even when being oxidized.
Transistors and a lower interlevel insulating film are formed on a silicon substrate prior to forming ferroelectric capacitors. After forming conductive plugs of W or the like extending through the lower interlevel insulating film and contacting transistors, ferroelectric capacitors are formed each having a lower electrode, a ferroelectric film and an upper electrode. It is necessary to prevent the oxidizing atmosphere during forming the ferroelectric film from adversely affecting the lower structure. Multilevel wirings are thereafter formed in upper interlevel insulating film.
An interlevel insulating film of a semiconductor integrated circuit device is often made of silicon oxide. Silicon oxide has high affinity with moisture. As moisture permeates from external, the moisture can pass through an interlevel insulating film and reach wirings, capacitors, transistors and the like. As the moisture reaches a capacitor, particularly a ferroelectric capacitor, characteristics of a dielectric film, particularly of a ferroelectric oxide film are degraded. If the ferroelectric film is reduced by hydrogen derived from the permeated moisture and oxygen defects are formed, crystallinity is degraded. Characteristics such as a coercive polarization amount and a dielectric constant are degraded. Similar phenomena occur due to long term usage. As hydrogen permeates, the characteristics are degraded more directly than moisture. Permeation of moisture and hydrogen is prevented by forming a cover film having moisture resistance on multilevel wirings and forming a moisture resistant ring along a semiconductor chip outer periphery. However, a bonding pad for inspection or external connection is required to be in exposed state.
In a semiconductor integrated circuit device having a moisture resistance ring, the area influenced most by moisture and hydrogen permeated from external is considered to be pad and its nearby area. For example, an interlevel insulating film such as a silicon oxide film, a silicon nitride film and a polyimide film are formed covering the uppermost wiring layer including pads. In order to allow electric contacts to the pads, the polyimide film, silicon nitride film and silicon oxide film on the pads are removed. Moisture and hydrogen from external can directly contact the pads.
JP-A-2003-174146 (applicant: Fujitsu Limited) proposes to form an upper electrode by a lamination of two types of noble metal oxide films. In order to avoid adverse effects of an oxidizing atmosphere during forming a ferroelectric film, transistors formed on a semiconductor substrate are covered with an insulating barrier film having an oxygen shielding function such as a silicon nitride film and a silicon oxynitride film. In order to prevent the characteristics of a ferroelectric capacitor during heat treatment in a reducing atmosphere, the ferroelectric capacitor is covered with an insulating barrier film having a hydrogen shielding function such as an alumina film.